Power Electronics & Embedded Firmware · IEEE Xplore PCIM Asia 2025

Inverter PWM Modulation & Real-Time FFT

An algorithmic pulse-width modulation framework for 2-level three-phase voltage source inverters. Simulates Sinusoidal PWM (SPWM), Third-Harmonic Injection (THIPWM), Space Vector PWM (SVPWM), and Discontinuous PWM (DPWM1), reducing inverter switching losses by 33% and extending DC-bus utilization by 15.5% on STM32 ARM Cortex-M4 hardware.

Source on GitHub → IEEE Xplore (PCIM Asia 2025) STM32 ARM Cortex-M4 Real Client-Side DFT/FFT 8 Tests Passing
DC Bus Utilization
+15.5%
SVPWM linear range extension
Switching Loss Cut
33.0%
DPWM1 60° phase clamping
Total Harmonic Dist
1.8%
Calculated live via client FFT
Hardware ISR
< 1.2 μs
STM32 TIM1 advanced timer
Research Grounding: IEEE PCIM Asia 2025 Publication. Co-authored "PWM Strategies for VSIs: Python-Based Analysis, Simulation and Hardware Deployment" (PCIM Asia 2025 / IEEE Xplore). Built during engineering tenure at STMicroelectronics, where algorithmic models were validated against hardware test benches using STM32 microcontrollers and high-voltage motor drive power boards.

1. Mathematical Foundations & Space Vector Geometry

Three-phase balanced voltages \((v_a, v_b, v_c)\) project onto a complex orthogonal stationary plane \((\alpha, \beta)\) via the Clarke transformation:

Clarke Stationary Reference Frame

\[ \begin{bmatrix} v_\alpha \\ v_\beta \end{bmatrix} = \frac{2}{3} \begin{bmatrix} 1 & -\frac{1}{2} & -\frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & -\frac{\sqrt{3}}{2} \end{bmatrix} \begin{bmatrix} v_a \\ v_b \\ v_c \end{bmatrix} \]

In pure Sinusoidal PWM (SPWM), the maximum modulation index without overmodulation is \(m_a = 1.0\), yielding fundamental line-to-line RMS voltage \(V_{LL} = \frac{\sqrt{3}}{2\sqrt{2}} V_{dc} \approx 0.612 V_{dc}\). Space Vector PWM adds an optimal zero-sequence triplen harmonic, extending the linear modulation ceiling by:

\[ m_{a, \max} = \frac{2}{\sqrt{3}} \approx 1.155 \quad (+15.5\% \text{ DC-Bus Utilization}) \]

Discontinuous PWM1 (DPWM1) clamps each inverter phase leg to the positive or negative DC rail for 60° of each fundamental cycle (120° total per cycle). Because no switching occurs during the clamped interval, total inverter switching cycles drop by exactly one-third: \[ \Delta P_{\text{sw}} = \frac{120^\circ}{360^\circ} = 33.33\% \]

2. Live Inverter Modulation Synthesizer & Real-Time FFT

Select modulation techniques and adjust the modulation index \(m_a\) and carrier frequency ratio \(m_f\). The browser computes switching pulses and performs a genuine client-side Discrete Fourier Transform (FFT) in real time.

Inverter Switching Pulse Synthesizer

Real-time switching pulse calculation and harmonic distortion analysis

LINEAR MODULATION (m_a ≤ 1.155)
Fundamental RMS (\(V_1\))
0.551 Vdc
First harmonic peak
Total Harmonic Distortion (THD)
4.2%
Computed live over 512 DFT bins
Inverter Switching Loss
100.0%
Nominal baseline switching

Phase A Reference Voltage vs Triangular Carrier Wave

Line-to-Line Inverter Voltage Switched Pulse Train (\(V_{ab}\))

Real-Time Discrete Fourier Transform (DFT) Harmonic Spectrum

Each bar is calculated via direct Fourier integration \(\sum_{n=0}^{N-1} v[n] e^{-j 2\pi k n / N}\) over the synthesized waveform. Note the fundamental at \(h=1\) and the high-frequency switching sidebands clustered around \(m_f\) and \(2m_f\).